1. Field of the Invention
The present invention relates to a integrated circuit memories, and more particularly to an integrated circuit memory which includes frequency multiplier and clock edge synchronizing circuit to prevent bus contention during memory bank switching operation.
2. Description of the Related Art
Computer systems commonly utilize a high performance microprocessor which accesses data in a memory. Typically, the microprocessor handles data at a much faster speed than the memory. A common technique for better utilizing the speed of the microprocessor is to furnish two memory banks connected to a shared data bus and to interleave data access operations between the two banks. However, by accessing the multiple memory banks in this manner, contention for the bus between the memory banks may occur, in which two memory banks attempt to drive data of opposite levels on the same common data line.
Contention occurs when one memory bank is not completely deactivated, holding its output in a low impedance state, before another bank is activated. Bus contention often results because one memory bank is simply faster than another bank. Typically, separate memory chips form respective memory banks in a structure which exacerbates the problem of bus contention since temperature, process and voltage variability between the chips leads to variability in the operating speeds of memory in the different banks. In fact, even timing of clock signals within a single bank can vary widely depending on process conditions.
An example of a bus contention condition is shown in FIGS. 1A, 1B and 1C in which FIG. 1A depicts the signals 10 and 12 on output enable lines that drive respective memory banks A and B. FIGS. 1B and 1C illustrate, in a highly schematic manner, respective data signals 20 and 30 generated by the output drivers of memory banks A and B. In FIG. 1B, point 22 illustrates the earliest time at which memory bank A is deactivated after activation, point 24 illustrates the latest time. Time interval 26 depicts the variation in memory bank deactivation time of memory bank A due to differences in voltage, temperature and silicon processing. In FIG. 1C, point 32 illustrates the earliest time at which memory bank B is activated after deactivation, point 34 illustrates the latest time. Time interval 36 depicts the variation in memory bank activation time of bank B due to differences in voltage, temperature and silicon processing. Performance of the memory circuits depends on the timing relationships of points 22, 24, 32 and 34. If memory bank A is deactivated long before bank B is activated, reliable bank switching occurs but speed performance is limited. If memory bank A is deactivated shortly before bank B is activated, reliable bank switching occurs and speed performance is enhanced. However, if memory bank A is deactivated after bank B is activated, both banks are simultaneously activated and operation of memory switching becomes unreliable.
FIG. 2, which illustrates the effect on the memory circuit when both memory banks A and B are simultaneously active, shows a final stage of an output driver 50 of memory bank A and a final stage of an output driver 60 of memory bank B, each of which has an output terminal connected to a common data line 80. The common data line 80, which is typically a metal trace on a PC board, is connected to bonding wire for communications outside the computer system. In memory bank A, pullup transistor 52 and pulldown transistor 54 are large transistors which draw a large current. Similarly, in memory bank B, pullup transistor 62 and pulldown transistor 64 are large transistors. If timing signals overlap so that memory banks A and B are activated at the same time, a condition can arise in which pullup transistor 62 of memory bank B is conductive while pulldown transistor 54 of memory bank A is conductive. Pullup transistor 52 of bank A and pulldown transistor 64 of bank B are not conductive. Under these conditions, a current path is formed from the power supply 70 of memory bank B through pullup transistor 62 out to the PC board and on to memory bank A pulldown transistor 54 to ground 72 inside bank A. A huge current spike is thus generated which causes a large noise spike but also can damage an integrated circuit chip if the current spike is sufficiently large and enduring.
Data line contention is thus a timing overlap difficulty which generates noise in the form of large, transient current spikes. Large current transients affect power supply and ground lines of the computer system to further create noise. Noise degrades the long term reliability of the memory banks connected to the data lines. Therefore a new approach is necessary to improve the accuracy of memory timing signals and to thereby improve noise performance.